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IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT IDT74ALVCH16901 UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/ CHECKERS AND BUS-HOLD
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in TSSOP package
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
* High Output Drivers: 24mA * Suitable for heavy loads
APPLICATIONS:
* 3.3V high speed systems * 3.3V and lower voltage computing systems
This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction. The ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA and ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver. The ALVCH16901 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16901 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
LEAB
1C LKENAB 2C LKENAB 2
1 32 3 30
2
CLKAB OEAB
35
OEBA
1A1-1A8 1APA R 1E RRB 2A1-2A8 2A PAR 2E RRB 28 36 5 61
18 A-Port Parity Generate and Check B Data
18-Bit Storage
18 QA B-Port Parity Generate and Check A Data 18
29 60 4
1B1-1B8 1BP AR 1E RRA 2B1-2A8 37 2BP AR 2E RRA
18 QB
18-Bit Storage
ODD/EVEN SEL
34 31 62
CLKBA
1C LKENBA 2C LKENBA
2
64 33 63
LEBA
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c)2000 Integrated Device Technology, Inc.
JUNE 2000
DSC-4582/1
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TSSOP TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100 VTERM(3) TSTG IOUT IIK IOK ICC ISS
Unit V V C mA mA mA mA
1CLKENAB
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1CLKENBA
LEAB CLKAB
1ERRA 1APAR
LEBA CLKBA
1ERRB 1BPAR
GND
1A1 1A2 1A3
GND
1B1 1B2 1B3
VCC
1A4 1A5 1A6
VCC
1B4 1B5 1B6
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
GND
1A7 1A8 2A1 2A2
GND
1B7 1B8 2B1 2B2
NOTE: 1. As applicable to the device type.
GND
2A3 2A4 2A5
GND
2B3 2B4 2B5
PIN DESCRIPTION
Pin Names OEAB OEBA LEAB LEBA xCLKENAB xCLKENBA CLKAB CLKBA xERRA xERRB xAPAR xBPAR ODD/EVEN SEL xAx xBx Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B 9-bit Clock Enables B-to-A 9-bit Clock Enables A-to-B Clock Input B-to-A Clock Input A Error-Signal Outputs B Error-Signal Outputs A Port Parities B Port Parities Parity Select Input Parity Enables A-to-B Data Inputs or B-to-A 3-State Outputs (1) B-to-A Data Inputs or A-to-B 3-State Outputs (1)
VCC
2A6 2A7 2A8
VCC
2B6 2B7 2B8
GND
2APAR 2ERRA
GND
2BPAR 2ERRB
OEAB SEL
2CLKENAB
OEBA ODD/EVEN
2CLKENBA
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
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IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE(1,2)
Inputs CLKENAB X X X H L L L L OEAB H L L L L L L L LEAB X H H L L L L L CLKAB X X X X L H xAx X L H X L H X X Outputs xBx Z L H B(3) L H B(3) B(4)
PARITY ENABLE
Inputs SEL OEBA OEAB
L L L L H H H H H L H L L L H H L H H L L H L H
Operation or Function
Parity is checked on port A and is generated on port B. Parity is checked on port B and is generated on port A. Parity is checked on port B and port A. Parity is generated on port A and B if device is in FF mode. Parity functions are QA data to B, QB data to A disabled; device acts as QB data to A a standard 18-bit QA data to B registered transceiver. Isolation
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition 2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKENBA. 3. Output level before the indicated steady-state conditions were established. 4. Output level before the indicated steady-state conditions were established, provided that CLKAB was LOW before LEAB went LOW.
PARITY
SEL L L L L L L L L L L L L L L L L L L L L L L L L L L OEBA H H H H L L L L H H H H L L L L H H H H H H H H L L OEAB L L L L H H H H L L L L H H H H H H H H H H H H L L ODD/EVEN L L L L L L L L H H H H H H H H L L L L H H H H L H Inputs OF INPUTS A1--A8 = H - 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A Outputs OF INPUTS B1---B8 = H - N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A xAPAR L L H H N/A N/A N/A N/A L L H H N/A N/A N/A N/A L L H H L L H H N/A N/A xBPAR N/A N/A N/A N/A L L H H N/A N/A N/A N/A L L H H L L H H L L H H N/A N/A xAPAR N/A N/A N/A N/A L H L H N/A N/A N/A N/A H L H L N/A N/A N/A N/A N/A N/A N/A N/A PE(1) PO(2) xERRA H L L H Z Z Z Z L H H L Z Z Z Z H L L H L H H L Z Z xBPAR L H L H N/A N/A N/A N/A H L H L N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A PE(1) PO(2) xERRB Z Z Z Z H L L H Z Z Z Z L H H L H L L H L H H L Z Z
NOTES: 1. Parity output is set to the level so that the specific bus side is set to even parity. 2. Parity output is set to the level so that the specific bus side is set to odd parity.
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IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 - 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 22 5 VCC = 3.3V 0.3V Typical 27 8 Unit pF
5
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay xAx to xBx or xBx to xAx Propagation Delay xAx to xBPAR or xBx to xAPAR Propagation Delay xAPAR to xBPAR or xBPAR to xAPAR Propagation Delay xAPAR to xERRA or xBPAR to xERRB Propagation Delay ODD/EVEN to xERRB or xERRA Propagation Delay ODD/EVEN to xAPAR or xBPAR Propagation Delay SEL to xAPAR or xBPAR Propagation Delay LEBA to xAx or LEAB to xBx Propagation Delay LEBA to xAPAR or LEAB to xBPAR (parity feed through) Propagation Delay LEBA to xAPAR or LEAB to xBPAR (parity generated) Propagation Delay LEBA to xERRB or LEAB to xERRA Propagation Delay CLKBA to xAx or CLKAB to xBx Propagation Delay CLKBA to xAPAR or CLKAB to xBPAR(parity feed through) Propagation Delay CLKBA to xAPAR or CLKAB to xBPAR(parity generated) Propagation Delay CLKBA to xERRB or CLKAB to x ERRA Min. 125 1 2 1 2 1.5 1.5 1 1 1.5 2.5 2.5 1 1.5 2.5 2.5 Max. -- 5.2 8.9 5.7 9.7 8.7 8.3 6.1 6 6.7 9.8 9.9 6.4 7.1 10.2 10.5 VCC = 2.7V Min. 125 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- 4.8 7.6 5.2 8.7 7.9 7.6 5.9 5.5 6 8.3 8.5 5.8 6.3 8.7 8.9 VCC = 3.3V 0.3V Min. 125 1 2 1 2 1.5 1.5 1 1 1.5 2 2 1 1.5 2 2 Max. -- 4.4 6.7 4.7 7.5 6.8 6.5 5.1 4.8 5.3 7.4 7.5 5.1 5.6 7.7 7.9 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS (CONTINUED)(1)
VCC = 2.5V 0.2V Symbol tPZH tPZL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tPHZ tPLZ tSU tSU tSU tH tH tH tW tW tSK(o) Parameter Output Enable Time OEAB or OEBA to xBx, xBPAR or xAx, xAPAR Output Enable Time OEAB or OEBA to xERRA or xERRB Output Enable Time SEL to xERRA or xERRB Output Disable Time OEAB or OEBA to xBx, xBPAR or xAx, xAPAR Output Disable Time OEAB or OEBA to xERRA or xERRB Output Disable Time SEL to xERRA or xERRB Set-up Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR before CLK Set-up Time, HIGH or LOW, xCLKENAB or xCLKENBA before CLK Set-up Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR before LE Hold Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR after CLK Hold Time, HIGH or LOW, xCLKENAB or xCLKENBA after CLK Hold Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR after LE Pulse Width LEAB or LEBA HIGH Pulse Width CLKAB or CLKBA HIGH or LOW Output Skew(2) Min. 1.4 1.4 1.4 1.3 1.3 1.3 1.9 2.1 1.4 0.4 0.5 0.9 3 3 -- Max. 6.3 6.2 6.7 6.1 7.3 6.4 -- -- -- -- -- -- -- -- -- VCC = 2.7V Min. -- -- -- -- -- -- 2 2.1 1.3 0.4 0.5 1.1 3 3 -- Max. 6.1 5.5 6.5 5.2 6.5 5.4 -- -- -- -- -- -- -- -- -- VCC = 3.3V 0.3V Min. 1 1 1 1.5 1 1.5 1.7 1.7 1.2 0.5 0.7 0.9 3 3 -- Max. 5.3 4.9 5.5 4.9 5.7 4.9 -- -- -- -- -- -- -- -- 500 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND
VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC Link
VIN D.U.T. RT
VOUT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
Set-up, Hold, and Release Times
OUTPUT 1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
tSK (x)
tSK (x)
OUTPUT 2 tPLH2 tPHL2
VT
ALVC Link
Pulse Width
ALVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
8
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX ALVC X Bus-Hold Temp. Range XXX Family XXX XX Device Type Package
PA 901 16 H 74
Thin Shrink Small Outline Package 18-Bit Universal Bus Transceiver with Parity Generators/Checkers Double-Density, 24mA Bus-Hold -40C to +85C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
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for Tech Support: logichelp@idt.com (408) 654-6459
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